Hi, I'm Alex
About
I am Tulbure Alexandru Nicolae, a Computer and Information Technology engineer from Timișoara, Romania, currently pursuing two master's degrees in parallel: Machine Learning at the Politehnica University of Timișoara and Cybersecurity at the West University of Timișoara. Although I am primarily a Platform Engineer, specializing in building scalable and robust backend systems, I also do enjoy working on the Frontend side of things. Additionally, I have a passion for content writing and conducting research on various topics, particularly in the fields of Artificial Intelligence and System Architecture.
Work Experience
OPSWAT
- Joined OPSWAT as a Part-time Associate Software Engineer in June, 2025.
- Began my journey with OPSWAT through LigaLabs, a 3-month program by Politehnica University of Timișoara that connects students with industry opportunities.
- Continued as an Associate Software Engineer, working on an Email Phishing Detection project.
AUMOVIO
- A three-month internship (April – July 2023) through Liga AC Labs, the industry programme run by Politehnica University of Timișoara.
- Implemented and analysed core automotive functionalities in C, working hands-on with embedded systems concepts and automotive software development practices.
Education
Politehnica University of Timișoara
West University of Timișoara
Politehnica University of Timișoara
Grigore Moisil Theoretical High School
Skills
Projects
I like to build projects. I have built a lot of projects, here are just some of my favorites.

TripleA — Argus · Aegis · Athena
Bachelor thesis platform, graded 10/10: two native detection engines plus an explainer, behind a single web interface. Argus classifies files, Aegis classifies URLs, and Athena turns each verdict into plain language. Every result sits side by side with the MetaDefender equivalent — Argus against its 21-engine multiscan, Aegis against its aggregated URL reputation.

Argus — File Detection Engine
A native multi-layer file scanning engine (Rust cdylib, shipped as argus.so/argus.dll) that fuses three layers into one verdict: hash and reputation lookups in LMDB, deterministic byte-pattern and fuzzy-similarity signatures, and an XGBoost model exported to ONNX and routed per file format by a selector. Format-aware PE and PDF parsers build the feature vector, and hyperlinks embedded inside documents are scored too. Standalone evaluation reaches F1 0.97–0.98 and ROC-AUC above 0.99 for both formats.

Aegis — URL Classification Engine
A native URL-classification engine (Rust cdylib) that reduces a URL to a canonical 107-feature lexical vector — structural, character, length, entropy, ratio and security signals — and scores it through an XGBoost model exported to ONNX, returning Clean / Suspicious / Infected without ever fetching the target page. Trained on nine public corpora deduplicated into a single set; F1 ≈ 0.96, ROC-AUC ≈ 0.99. Also embedded inside Argus to score hyperlinks found in documents.

Athena — RAG Security Assistant
The component that makes a verdict intelligible: a retrieval-augmented assistant answering questions over OPSWAT documentation and live scan results. Query rewriting contextualises follow-ups, hybrid dense + sparse retrieval over Qdrant fuses results with RRF, a cross-encoder reranks them, parent-child assembly builds the context, and a 24h Redis cache fronts generation — with Prometheus timings on every stage.

ML Training Pipeline
The model supply chain behind both engines: a ten-step DAG covering feature extraction, filtering, statistical profiling, Optuna tuning (a cold search then a warm-started refinement), XGBoost training, SHAP explainability, ONNX export and held-out evaluation — running either as an AWS SageMaker Pipeline or as local subprocesses. Feature parity is guaranteed by construction: the engine's own Rust extractor is vendored in and called through ctypes, so training sees exactly the features production computes.

DarkRISCV — RV32I Soft-Core CPU
A working RISC-V RV32I processor written from scratch in Verilog, with a three-stage fetch/decode/execute pipeline wrapped into a System-on-Chip — memory, serial port, timer and LEDs — targeting a Terasic DE2 Cyclone II FPGA and simulatable on any PC with Icarus Verilog. Documented for readers meeting processor design for the first time.
